1. Field of the Invention
The present invention relates to a manufacturing apparatus of a wiring substrate and a manufacturing process for a wiring substrate using the apparatus, and particularly, to a polishing and manufacturing apparatus and a process for selectively forming a wiring substrate consisting of a copper or copper-based alloy (hereinafter referred to as xe2x80x9cCuxe2x80x9d) and a diffusion preventing layer (xe2x80x9cbarrier layerxe2x80x9d) for Cu.
2. Description of the Related Art
In recent years, replacement of interconnects using an aluminum alloy (which will hereinafter be abbreviated as xe2x80x9cAlxe2x80x9d) with Cu interconnects has started in order to satisfy the requirement for speeding-up of large-scale semiconductor integrated circuits (abbreviated as xe2x80x9cLSIxe2x80x9d). Cu interconnects are usually, formed by the damascene method. In this method, as described in JP-A No. 278822/1990, a hole or trench (hereinafter referred to collectively as a xe2x80x9ctrenchxe2x80x9d) is made in advance in an insulating film; a thin barrier layer made of tantalum (Ta) or tantalum nitride (TaN) for preventing Cu diffusion and improving adhesion is formed in the trench; a Cu layer is formed to embed the trench therewith; and the Cu layer and barrier layer at portions other than the trench are removed by chemical mechanical polishing (hereinafter referred to as CMP or xe2x80x9cpolishingxe2x80x9d), whereby a damascene Cu interconnect structure having the Cu layer and the barrier layer embedded only in the trench is formed.
After completion of polishing, however, Cu embedded in the insulating film is exposed directly from the surface of the polished wiring substrate. Although multilevel interconnection by using Cu requires formation of an insulating film over Cu, a silicon oxide (xe2x80x9cSiO2xe2x80x9d) film or many insulating films composed of other materials are not suited, because they are poor in adhesion with Cu and moreover, prompt diffusion of Cu occurs in such insulating films. There are not many insulating materials which can be formed directly on the Cu exposed surface of a wiring substrate, have adequate adhesion and suppress Cu diffusion. Currently, silicon nitride (xe2x80x9cSiNxe2x80x9d), silicon carbide (xe2x80x9cSiCxe2x80x9d) and the like are employed. They are however deficient in diffusion preventive capability and adhesion with Cu. Moreover, these materials have a high dielectric constant so that use of them increases electrostatic capacity between interconnects, thereby increasing the propagation delay of interconnect signals. In recent years, use of low-dielectric-constant materials as an insulating film for forming a trench therein has been studied in order to reduce electrostatic capacity between interconnects. The low-dielectric-constant material is usually low in density and diffusion rate of Cu therein is larger than in an SiO2 film. So, there is a high risk that a further deterioration in long-term reliability occurs in the Cu multilevel interconnection using a low-dielectric-constant material. The conventional method of covering a Cu polished surface with an insulating film made of a silicon compound restricts the ability to improve the wiring characteristics and prevents maintenance of sufficient long-term reliability.
As another countermeasure against the above-described problem, a method of forming a cobalt (Co)xe2x80x94tungsten (W) alloy (xe2x80x9cCoxe2x80x94W alloyxe2x80x9d) selectively on the Cu polished surface by electroless plating is described in xe2x80x9cProceedings of the Second International Symposium on Low and High Dielectric Constant Materials: Materials Science Processing and Reliability Issues (published by The Electrochemical Society), Vol. 97-8, 186-195xe2x80x9d. As illustrated in FIG. 3A, the wiring substrate 30 comprises a first insulating film 301 formed on a substrate 300 made of, for example, silicon, and after making an interconnect trench in the insulating film, a first barrier layer 303 and a first Cu interconnect layer 304 are embedded in the trench in order to improve adhesion with Cu and prevent diffusion of Cu. Polishing is usually employed for leaving the first Cu layer 304 and first barrier layer 303 only in the trench. By selective electroless plating, a barrier metal layer 305 is selectively formed over the Cu surface as illustrated in FIG. 3B (such a barrier metal layer formed by electroless plating will hereinafter be called xe2x80x9cplated barrier layerxe2x80x9d). Cobalt (Co) and nickel (Ni) are known materials of the plated barrier layer 305. In the electroless plating, an oxide on the surface of the underlying metal layer, for example, the first Cu interconnect layer 304 is etched or reduced, and depending on a slight difference in the chemical condition between the Cu surface and the peripheral surface of the first insulating film, particles for the formation of the plated barrier layer are precipitated only on the surface of the metal layer. Moreover, even within the surface of the Cu interconnect 304, precipitation of particles, which will constitute the plated barrier film 305, tends to occur easily at portions different in the state from the periphery, for example, so-called defective portions such as grain boundary or scratches generated during polishing. These precipitated particles are connected each other as illustrated in FIG. 3B, thereby forming a continuous plated barrier film 305 having a diffusion preventive capability against the Cu interconnect 304. To impart the plated barrier film 305 with sufficient Cu diffusion barrier effect, it was conventionally necessary to form the film having a thickness of 0.1 micron or greater. Such thickness of the plated barrier film 305 is too large where the Cu interconnect has the minimum processing dimension of about 0.2 micron or less. Only a slight difference exists in the chemical condition between the surface of the Cu interconnect 304 and the surface of the first insulating film 301 at the periphery thereof. If some pollutants or scratches exist on the surface of the first insulating film 301, abnormal growth particles 305b inevitably occur even at such defective portions. The conventional electroless plating therefore involves another problem that with the growth of the plated barrier film 305 as thick as 0.1 micron, the abnormal growth particles 305b increases, causing a short-circuits between interconnects and/or lower yields.
The conventional electroless plating is conducted in a manner as illustrated in FIG. 4. A plating vessel 43 stored in a heating tank 40 is filled with a plating solution 45 for a plated barrier layer. The solution is kept at a predetermined temperature by the heating tank 40. Electroless plating is usually conducted at 70 to 90xc2x0 C. The plating solution 45 is stirred by a stirring rod 44. A wiring substrate 46 which has been surface-treated in advance is immersed in the solution for forming a barrier layer by plating. Since the temperature of the plating solution 45 is high, evaporation and, in turn, a change in the composition of the solution tend to occur. In order to prevent them, hollow plastic balls 47 are floated all over the surface of the plating solution. In such a conventional electroless plating method, the above-described surface treatment is conducted as pre-treatment for the formation of a plated barrier layer selectively on the Cu surface. The effect of this pre-treatment for improving selectivity, however, depends only on the effect of chemical treatment of the wiring substrate 46 with an acid or alkali solution. Effects of this pretreatment for removing foreign matters adhered to the substrate or pollutants whose removal is not intended by the chemical solution are not sufficient and abnormal nuclear growth of the plated barrier layer on the first insulating film cannot be prevented fully. On the contrary, sufficient removal of the substances adhered to the Cu surface sometimes makes it difficult to allow particles to grow all over the metal surface.
In JP-A No. 22285/1998, proposed is an idea of simultaneously causing polishing and plating of the polished surface by adding components of a plating solution to a polishing solution containing abrasive powder (which will hereinafter be called xe2x80x9cslurryxe2x80x9d) for Cu upon processing of Cu interconnect by CMP. The slurry for metal needs to contain components which oxidize a metal surface (oxidative), while the plating solution needs to have reductive reaction of the metal surface. Soon after mixture, they react with each other so that such a mixture can hardly be used as a stable treating solution. The kinds of plating solutions that can be added to the slurry are limited to those for plating metals, such as gold and tin, which are reactive with Cu and have low melting points. Accordingly, heat-resistant Cu diffusion barrier effect cannot be attained by plating of Cu with such a metal material. Moreover, a conventionally known electroless plating solution contains a large amount of sodium ions. Upon electroless plating conducted within a temperature range of from 70 to 90xc2x0 C., sodium ions diffuse quickly in a wiring substrate, thereby deteriorating the characteristics of each element formed on the wiring substrate. This adverse effect cannot be removed easily only by washing after electroless plating. Furthermore, an electroless plating solution usually needs a temperature control at 70 to 90xc2x0 C., while CMP of Cu is conducted at room temperature of 20 to 30xc2x0 C. It is therefore difficult to simultaneously perform CMP and plating under suitable conditions by using, as a mixture, a slurry for CMP and a plating solution. Even if CMP is conducted at a temperature as high as 70 to 90xc2x0 C. suited for plating, severe corrosion of Cu occurs, disturbing high-precision polishing. CMP at about room temperature of 20 to 30xc2x0 C., on the other hand, disturbs formation of a plated barrier layer.
In the conventional electroless plating, as illustrated in FIG. 5, there usually exists some suppressing time (which will hereinafter be called xe2x80x9cincubation periodxe2x80x9d) from the time of immersion of the wiring substrate in a plating solution until starting of the precipitation of a plated barrier layer in practice. The reason why such incubation period exists has not been made clear. This incubation time, however, varies greatly even within the wiring substrate or among wiring substrates, resulting in large variations in the thickness of the plated barrier film thus formed. In order to attain reliability necessary all over the surface of the wiring substrate, a markedly thick plated barrier film must be formed, leading to a deterioration in the flatness on the surfaces of interconnects, short-circuits between interconnects and an increase in the wiring resistance in multilevel interconnection.
To summarize, conventional electroless plating involves, in addition to necessity of a thick plated barrier layer and therefore unsuitability to minute Cu interconnects, the following drawbacks: (1) it tends to cause short-circuits between interconnects, (2) a stable plated barrier layer cannot be formed easily, (3) there tends to occur variations in the film thickness of the plated barrier layer within the wiring substrate or between wiring substrates, and (4) sodium ions contained in the barrier plating solution deteriorate the characteristics of the elements. Owing to such problems, it is not suited as a practically usable technique. It is necessary to suppress variations or instability in, the conventional electroless plating in order to apply it as a practical technique for the formation of a plated barrier layer.
The present invention provides a method capable of (1) forming a thin plated barrier layer which exhibits a diffusion preventive effect in spite of such a thin film thickness; (2) reducing variations in the thickness of the plated barrier layer within the wiring substrate or between wiring substrates, (3) suppressing the growth of a film formed by plating (xe2x80x9cplated filmxe2x80x9d) at a portion other than the wiring portion, thereby preventing the abnormal growth of particles which will otherwise be a foreign matter causing short-circuits between interconnects or a reduction of the yield. It is preferable upon carrying out the present invention that the sodium ions, which cause the deterioration in the characteristics of the semiconductor device, are removed from the plating solution to the maximum extent practical.
As shown in FIG. 2A, the surface of the wiring substrate 15 is preferably cleaned, as pretreatment, by sliding the substrate while pressing it against a resin pad 13 and pouring a cleaning liquid onto it. Then, plating is carried out selectively on the surface of a metal by forming a barrier layer while pressing the wiring substrate against the surface of a resin pad at a predetermined pressure, rotating it and feeding it with a plating solution. Upon plating, by keeping the wiring substrate as warm as the plating solution and maintaining the plating atmosphere less-oxidative in order to stabilize the growth of a film. An electroless plating apparatus developed newly for the above-described purpose, an electroless plating solution for a plating barrier in which sodium-ions are not included as a component material and a newly developed plating process make it possible to form a plated barrier layer which has markedly high stability and excellent Cu diffusion preventive effect.
The present invention provides a technique for forming a thin plated barrier layer resistant to Cu diffusion and excellent in barrier property by using a plating apparatus capable of suppressing film growth at a portion other than a metal layer. By using a sliding-type plating apparatus which has controlled the temperature of each of the wiring substrate, the resin pad and the plating solution to be supplied, it becomes possible to reduce the probability of the generation of foreign matters which will be causative of short-circuits between interconnects or lower yields. Moreover, fluctuations in the film thickness can be reduced by allowing the barrier layer to grow for a predetermined period of time after irradiating a light onto a wiring substrate and detecting the plating starting point by an optical means.